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APPLICATION NOTE A V A I LABLE
AN56
High Speed NOVRAM
FEATURES * Fast access time: 35ns * High reliability --Endurance: 105 nonvolatile store operations --Retention: 10 years minimum * Power-on recall --EEPROM data automatically recalled into RAM upon power-up * Low power CMOS --Standby: 1mA * Infinite EEPROM array recall, and RAM read and write cycles * Hardware store initiation (store cycle time < 10ms) * Available in the 32-lead plastic leadless chip carrier package DESCRIPTION
X20CZ16
The Xicor X20CZ16 is a 2K x 8 NOVRAM featuring a high-speed static RAM overlaid bit-for-bit with a nonvolatile electrically erasable PROM (EEPROM). The X20CZ16 is fabricated with advanced CMOS floating gate technology to achieve high speed with low power and wide power-supply margin. The NOVRAM design allows data to be easily transferred from RAM to EEPROM (store) and EEPROM to RAM (recall). The store operation is completed in 10ms or less and the recall operation is completed in 20s or less. An automatic array recall operation reloads the contents of the EEPROM into RAM upon power-up. Xicor NOVRAMS are designed for unlimited write operations to RAM, either from the host or recalls from EEPROM, and a minimum 100,000 store operations to the EEPROM. Data retention is specified to be greater than 10 years.
FUNCTIONAL DIAGRAM
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
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P
EEPROM Array
O R
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E EC AL L
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Store/ Recall Control
Address Decoder
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SRAM Array
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DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
Data I/O Input Buffers
R
ST
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Read/Write/ Store Logic
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Characteristics subject to change without notice.
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VCC VSS VCC OE NE CE WE
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X20CZ16
PIN CONFIGURATION
PLCC VCC WE NC NC NC NE A7
4 A6 A5 A4 A3 A2 A1 A0 NC I/O0 5 6 7 8 9 10 11 12
3
2
1 32 31 30 29 28 27 26 A8 A9 NC NC OE A10 CE I/O7 I/O6
X20CZ16 (TOP VIEW)
25 24 23 22
13 21 14 15 16 17 18 19 20 I/O1 I/O2 VSS I/O3 I/O4 I/O5 NC
ORDERING INFORMATION
Part Number
X20CE16JI-35
-35 = 35 ns
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+5V Ground
Access Time
P
Temperature Range
-40C to 85C
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Package
J = 32-Lead PLCC
PIN DESCRIPTIONS PLCC
et
Symbol
A0-A10 WE CE OE NE VCC VSS NC Address inputs Data input/output Write enable Chip enable Output enable Nonvolatile enable I/O0-I/O7 No connect
11, 10, 9, 8, 7, 6, 5, 4, 29, 28, 24 13, 14, 15, 18, 19, 20, 21, 22 31 23 25 2 32 16
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1, 3, 12, 17, 26, 27, 30
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Description
Characteristics subject to change without notice.
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X20CZ16
ABSOLUTE MAXIMUM RATINGS* Temperature under bias ................... -65C to +135C Storage temperature ....................... -65C to +150C Voltage on any pin with respect to VSS .......................... -0.3V to VCC + 0.5V D.C. output current ............................................. 10mA Lead temperature (soldering, 10 seconds)........ 300C Power Supply Voltage (VCC to VSS) .....-0.5V to +7.0V RECOMMENDED OPERATING CONDITIONS Temperature
Industrial
*COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any conditions other than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Min.
-40C
Max.
+85C
Supply Voltage
X20CZ16
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All inputs = VIH All I/Os = open VIN = VSS to VCC IOL = 4mA IOH = -4mA
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.) Limits Symbol
lCC1
Parameter
VCC current (active)
Min.
P
Max.
100 7 27 1 10 10 0.8 VCC + 0.3 0.4 7 8
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Unit
mA mA mA mA A A V V V V
Test Conditions
NE = WE = VIH, CE = OE = VIL Address inputs = 0.4V/2.4V levels @ f = 20MHz All I/Os = open
ICC2 ISB1 ISB2 ILI ILO VIL(1) VIH
(1)
VCC current during store VCC standby current (TTL input)
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-0.3 2.2 2.4
VCC standby current (CMOS input)
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CE = VIH, All other inputs = VIH All I/Os = open All inputs = VCC - 0.3V All I/Os = open VOUT = VSS to VCC, CE = VIH
Output leakage current Input LOW voltage Input HIGH voltage
VOL
VOH
CAPACITANCE TA = +25C, f = 1MHz, VCC = 5V
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Symbol
CI/O(2) CIN
(2)
bs
Output LOW voltage Output HIGH voltage
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Input leakage current
Test
Input/output capacitance Input capacitance
Max.
Unit
pF pF
Notes: (1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested.
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Characteristics subject to change without notice.
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Limits
5V 10%
Conditions
VI/O = 0V VIN = 0V
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X20CZ16
ENDURANCE AND DATA RETENTION Parameter
Store cycles Data retention
Min.
100,000 10
Unit
Store cycles
MODE SELECTION CE
H L L L L L L L L
WE
X H L L H L H L H
NE
X H H H L L H L L
OE
X L H H L H H L H
Mode
Not selected Read RAM Write "1" RAM Write "0" RAM Array recall Nonvolatile store Output disabled Not allowed No operation
I/O
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INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don't Care: Changes Allowed N/A Will be steady
Output high Z Output data
Input data high Input data low Output high Z Output high Z
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Output high Z Output high Z
P
Output high Z
EQUIVALENT A.C. LOAD CIRCUIT
5V
e
A.C. CONDITIONS OF TEST
Input pulse levels Input rise and fall times Input and output timing levels 0V to 3V 5ns 1.5V
735K Output
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SYMBOL TABLE
WAVEFORM OUTPUTS
318
30pF
bs
Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance
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Characteristics subject to change without notice.
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Power
Active Active Active Active Active Active Active Active Standby
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X20CZ16
A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified) Read Cycle Limits X20CZ16-35 -40 to +85C Symbol
tRC
(3)
Parameter
Read cycle time Chip enable access time Address access time Output enable access time Chip enable to output in low Z Output enable to output in low Z Chip disable to output in high Z Output disable to output in high Z Output hold from address change
Min.
35
tCE tAA tOE tLZ(3) tOLZ tHZ
(3) (3) (3)
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5 0
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tOH tAA
0
tOHZ tOH
Note:
0 3
(3)
Read Cycle
tRC Address
CE
OE
bs
WE
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tCE
tOE
tOLZ tLZ Data Valid tHZ Data Valid
e
P
(3) These parameters are periodically sampled and not 100% tested. tHZ max. and tOHZ max. are measured, with CL = 5pF, from the point when CE or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven.
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Data I/O
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Max.
35 35
Unit
ns ns ns
20
ns ns ns ns ns ns
15
15
tOHZ
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X20CZ16
Write Cycle Limits X20CZ16-35 Symbol
tWC
(4)
Parameter
Write cycle time Chip enable to end of write input Address setup time Write pulse width Write recovery time Data setup to end of write Data hold time Write enable to output in high Z Output active from end of write Output enable to output in high Z
Min.
35 30 0 30 0 30 0
Max.
Unit
ns ns
tCW tAS tWP tWR tDW tDH tWZ
(4) (4)
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tWP tDW Data Valid tDH
tOW
5
tOZ(4)
Note:
(4) These parameters are periodically sampled and not 100% tested.
WE Controlled Write Cycle
Address
OE
et
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CE
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tAS
P
tWC tCW tWR tOZ tOW
Data Out
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Data In
bs
WE
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Characteristics subject to change without notice.
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ns ns ns ns ns ns ns ns 15 20
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X20CZ16
CE Controlled Write Cycle
tWC
OE
VIH tCW
CE tAS WE tWZ Data Out tWP
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tDW Data Valid
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Data In
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tWR tOW tDH
Characteristics subject to change without notice.
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Address
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X20CZ16
ARRAY RECALL CYCLE LIMITS(6) X20CZ16-35 Symbol
tRCC tRCP
(5)
Parameter
Array recall cycle time Recall pulse width to initiate recall WE setup time to NE OE setup time to NE CE setup time to NE
Min.
30 5 5 5
Max.
20
Unit
s ns
tRWE tROE tRCE
du
Array Recall Cycle
tRCC Address tRCP NE
OE
WE
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CE
Data I/O
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tRWE
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tROE
tRCE
P
Characteristics subject to change without notice.
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Notes: (5) The Recall Pulse Width (tRCP) is a minimum time that NE, OE and CE must be LOW simultaneously to insure data integrity, NE and CE. (6) The limits shown are for NE initiated recall. The setup times and pulse width requirements for the active signals in CE initiated and OE initiated recalls are identical.
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ns ns ns
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X20CZ16
STORE CYCLES X20CZ16-35 Symbol
tWLQX tWLNH tGHNL tNLWL tELWL STORE cycle time STORE initiation cycle time Output disable setup to NE fall NE setup Chip enable setup 30 5 5 5
Store Cycle WE-controlled
Min.
Max.
10
Unit
ms ns ns
du
tNLWL tELWL
Store Cycle: WE Controlled
NE
OE tGHNL
WE
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CE
e
P
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Data I/O
O
bs
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tWLNH tWLQX
Characteristics subject to change without notice.
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ns ns
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X20CZ16
X20CZ16-35 Symbol
tELQXS tELNHS tGHEL tNLEL tWLEL STORE cycle time STORE initiation cycle time Output disable setup to CE fall NE setup Write enable setup 30 5 5 5
Store Cycle CE-controlled
Min.
Max.
10
Unit
ms ns ns
Store Cycle: CE Controlled
tNLEL NE
OE
tGHEL tWLEL
WE
CE
e
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tELNHS tELQXS
Data I/O
Symbol
tRESTORE VSWITCH
Note:
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STORE CYCLE INHIBIT AND AUTOMATIC POWER UP RECALL Store Cycle Inhibit and Automatic Power Up RECALL
duration(7)(2) 4.0
et
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Min. Max.
650 4.5
du
Unit
s V
t tRESTORE STORE inhibit
Power up RECALL
bs
Low voltage trigger level
(7) tRESTORE starts from the time VCC rises above VSWITCH.
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VCC 5.0V VSWITCH
Power Up RECALL
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Characteristics subject to change without notice.
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ns ns
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X20CZ16
DETAILED PIN DESCRIPTIONS Addresses (A0-A10) The Address inputs select an 8-bit memory location during a read or write operation. Chip Enable (CE) The Chip Enable input must be LOW to enable all read/ write operations. When CE is HIGH, power consumption is reduced. Output Enable (OE) The Output Enable input controls the data output buffers and is used to initiate read and recall operations. Output Enable LOW disables a store operation regardless of the state of CE, WE, or NE. Data In/Data Out (I/O0-I/O7) Data is written to or read from the X20CZ16 through the I/O pins. The I/O pins are placed in the high impedance state when either CE or OE is HIGH or when NE is LOW. Write Enable (WE) The Write Enable input controls the writing of data to the static RAM. Nonvolatile Enable (NE) The Nonvolatile Enable input controls the store and recall function to the EEPROM array. DEVICE OPERATION SRAM Read The X20CZ16 performs a READ cycle whenever CE and OE are LOW while WE and NE are HIGH. The address specified on pads A0-A10 determines which of the 2048 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tRC. If the READ is initiated by CE or OE, the outputs will be valid at tCE or at tOE, whichever is later. The data outputs will repeatedly respond to address changes within the tRC access time without the need for transition on any control input pins, and will remain valid until another address change or until CE or OE is brought HIGH or WE or NE is brought LOW. SRAM Write A WRITE cycle is performed whenever CE and WE are LOW and NE is HIGH. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either CE or WE goes HIGH at the end of the cycle. The data on pins DQ0-7 will be written into the memory if it is valid tDW before the end of a WE controlled WRITE or tDW before the end of a CE controlled WRITE. It is recommended that OE is kept HIGH during the entire WRITE cycle to avoid data bus contention on the common I/O lines. If OE is left LOW, internal circuitry will turn off the output buffers tWZ after WE goes LOW. Noise Consideration The X20CZ16 is a high speed memory and therefore must have a high frequency bypass capacitor of approximately 0.1 F connected between VCC and VSS using leads and traces that are as short as possible. As with all high speed CMOS ICs, normal careful routing of power, ground and signals will help prevent noise problems. Hardware Nonvolatile STORE A STORE cycle is performed when NE , CE and WE are LOW while OE is HIGH. While any sequence to achieve this state will initiate a STORE, only WE initiation and CE initiation are practical without risking an unintentional SRAM WRITE that would disturb SRAM data. During a STORE cycle, previous nonvolatile data is erased the SRAM contents are then programmed into nonvolatile elements. Once a STORE cycle is initiated, further input and output is disabled and the DQ0-7 pins are tristated until the cycle is completed.
Characteristics subject to change without notice.
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The X20CZ16 has two separate modes of operation: SRAM mode and nonvolatile mode, determined by the state of the NE pin. In SRAM mode, the memory operates as a standard fast static RAM. In nonvolatile mode, data is transferred from SRAM to EEPROM (the STORE operation) or from EEPROM to SRAM (the RECALL operation). In this mode SRAM functions are disabled.
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X20CZ16
If CE and OE are LOW and WE and NE are HIGH at the end of the cycle, a READ will be performed and the outputs will go active, indicating the end of the STORE. Hardware Nonvolatile RECALL A RECALL cycle is performed when CE, OE and NE are LOW while WE is HIGH. Like the STORE cycle, RECALL is initiated when the last of the three clocksignals goes to the RECALL state. Once initiated, the RECALL cycle will complete, during which all inputs are ignored. When the RECALL completes, any READ or WRITE state on the input pins will take effect. Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells. The RECALL in no way alters the data in the nonvolatile cells. The nonvolatile data can be recalled an unlimited number of times. Like the STORE cycle, a transition must occur on some control pins to cause a RECALL, preventing inadvertent multi-triggering. Automatic Power Up RECALL On power up, once VCC exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated. The voltage on the VCC pin must not drop below VSWITCH once it has risen above it in order for the RECALL to operate properly. Due to this automatic RECALL, SRAM operation cannot commence until tRESTORE after VCC exceeds VSWITCH. If the X20CZ16 is in a WRITE state at the end of power up RECALL, the SRAM data will be corrupted. Hardware Protection The X20CZ16 offers two levels of protection to suppress inadvertent STORE cycles. If the control signals (CE, OE, WE and NE) remain in the STORE condition at the end of a STORE cycle, a second STORE cycle will not be started. The STORE (or RECALL) will be initiated only after a transition on any one of these signals to the required state. In addition to multi-trigger protection, the X20CZ16 offers hardware protection through VCC Sense. When VCC < VSWITCH the externally initiated STORE operation will be inhibited. Low Average Active Power The X20CZ16 has been designed to draw significantly less power when WE is LOW (chip enabled) but the access cycle time is longer than 55 ns. When WE is HIGH the chip consumes only standby current. The overall average current drawn by the part depends on the following items: 1. CMOS or TTL input levels 2. The time during which the chip is disabled (CE HIGH) 3. The cycle time for accesses (CE LOW) 4. The ratio of READs to WRITEs 5. The operating temperature 6. The VCC level
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To help avoid this situation, a 10 K resistor should be connected between WE and system VCC.
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Characteristics subject to change without notice.
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X20CZ16
PACKAGING INFORMATION
32-Lead Plastic, PLCC, Package Code J32
0.420 (10.67)
0.510" Typical 0.400" 0.050 (1.27) Typ.
0.021 (0.53) 0.045 (1.14) x 45
0.013 (0.33) Typ. 0.017 (0.43)
P
et
0.495 (12.57) 0.485 (12.32) Typ. 0.490 (12.45)
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0.595 (15.11) 0.585 (14.86) Typ. 0.590 (14.99) 0.553 (14.05) 0.547 (13.89) Typ. 0.550 (13.97) 0.400 Ref. (10.16)
Pin 1
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0.453 (11.51) 0.447 (11.35) Typ. 0.450 (11.43) 0.300 (7.62) Ref.
NOTES: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY
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FOOTPRINT
Seating Plane 0.004 Lead CO - Planarity -- 0.015 (0.38) 0.095 (2.41) 0.060 (1.52)
0.140 (3.56) 0.100 (2.45) Typ. 0.136 (3.45) 0.048 (1.22) 0.042 (1.07)
3 Typ.
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0.300" Ref. 0.410"
0.050" Typical
0.030" Typical 32 Places
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Characteristics subject to change without notice.
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0.050" Typical 13 of 14
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X20CZ16
LIMITED WARRANT
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(c)Xicor, Inc. 2003 Patents Pending
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. COPYRIGHTS AND TRADEMARKS
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Xicor, Inc., the Xicor logo, E2POT, XDCP, XBGA, Direct Write cell, Concurrent Read-Write, PASS, MPS, PushPOT, Block Lock, IdentiPROM, E2KEY, X24C16, SecureFlash, and SerialFlash are all trademarks or registered trademarks of Xicor, Inc. All other brand and product names mentioned herein are used for identification purposes only, and are trademarks or registered trademarks of their respective holders. U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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